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w6612 dual pcm codec publication release date: october 1998 - 1 - revision a1 table of contents- 1. general description......................................................................................................... .... 2 2. features.................................................................................................................... ................ 2 3. pin configuration ........................................................................................................... ....... 3 4. pin descriptions ............................................................................................................ ......... 3 4.1. power control interface ................................................................................................... ....................3 4.2. analog interface.......................................................................................................... .........................4 4.3. pcm serial interface...................................................................................................... ......................5 5. block diagram ............................................................................................................... .......... 7 6. functional descriptions..................................................................................................... 7 6.1. power supply management system............................................................................................ ........7 6.2. ? codec-filter .................................................................................................................. ...................8 6.3. data conversion ........................................................................................................... .......................8 6.4. sequence and control ...................................................................................................... .................11 6.5. i/o level................................................................................................................. ............................12 7. electrical characteristics............................................................................................. 12 7.1. absolute maximum ratings.................................................................................................. ..............12 7.2. dc characteristics ........................................................................................................ .....................12 7.3. analog transmission characteristics ....................................................................................... ..........13 7.4. analog electrical characteristics......................................................................................... ...............14 7.5. digital switching characteristics ......................................................................................... ...............15 8. application information.................................................................................................... 1 8 9. package dimensions .......................................................................................................... .. 20
w6612 - 2 - 1. general description the winbond dual pcm codec is a 2 channel chip incorporating two ? pcm codec filter complying with the 64k bps a/mu law specified in ccitt g.711 standard. in addition, this chip also meets the pcm conformance specification of the ccitt g.714 recommendation. this chip is operated at 5 volts typically. it consists of some dual op amplifiers integrated with a ? pcm codec-filter to allow for easy control of the input/output analog interface. and the device also includes dual serial data port(sdp) to access the digital a/d and d/a data. 2. features ? single 5.0 volt power supply ? master clock rate: 2.048 mhz, or 1.536 mhz ? power comsumption of 19 ma for 5 volt; power down of 0.2 ma for 5 volt ? dual linear 14 bits ? pcm codec-filter for a/d and d/a converters ? full-duplex 2 channel speech codec ? complete a/mu-law companding or 14 bit linear output ? meet pcm conformance spec. of ccitt g.712/g.714 ? 3 types transfer rate: long frame, short frame and gci(general circuit interface) ? serial pcm transfer data rate from 128 to 4096 kbps for long frame and short frame ? serial pcm transfer data rate from 512 to 4096 kbps for gci frame interface ? separate power down mode ? dual analog input op. amplifier with external gain adjust ? dual analog ouput ? single-end power driver with 2k ? load ? differential power driver with 300 ? load and external gain adjust ? 2.7 volt regulator for digital circuit ? packaged in 44-pin pqfp
w6612 publication release date: october 1998 - 3 - revision a1 3. pin configuration winbond dual pcm codec (pqfp) 44 43 42 41 40 39 23 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 1 2 3 4 5 6 7 8 9 10 11 22 12 13 14 15 16 17 18 19 20 21 gnda1 p o 1 + p o 1 - pi 1 r o 1 v a a 1 t s t 1 t s t 2 t s t 3 p d i 1 v d d tg1 t1- t1+ vag v d s p p o 2 + p o 2 - pi 2 ro2 gnda2 tg2 t2- t2+ vaa2 g n d d m o d e 0 m o d e 1 d r 2 b c l k r 2 f s r 2 n c dt2 fst2 bclkt2 dr1 fsr1 bclkr1 nc dt1 fst1 bclkt1 mclk p d i 2 figure 3-1 dual pcm codec pin assignment 4. pin descriptions 4.1. power control interface pin name pin no. i/o function v dd 34 i this pin is the digital power supply at 5 volt. this pin should be decoupled to gndd with a 0.1 f capacitor. vdsp 39 o this is the output of the on-chip 2.7 volt regulator which supplies the digital circuit of the chip. this pin should be decoupled to gnda2 with a 0.1 f ceramic capacitor. this pin cannot be used for powering external loads. gndd 35 i this pin connects the digital ground and is typically connected to 0 volt. vaa1 40 i this pin is the first analog power supply at 5 volt. this pin should be decoupled to gnda1 with a 0.1 f capacitor.
w6612 - 4 - 4.1. power control interface, continued pin name pin no. i/o function vaa2 5 i this pin is the second analog power supply at 5 volt. this pin should be decoupled to gnda2 with a 0.1 f capacitor. gnda1 1 i this pin connects the first analog ground and is typically connected to 0 volt. gnda2 10 i this pin connects the second analog ground and is typically connected to 0 volt. vag 6 o this is the analog signal reference ground output pin which supplies a 2.5 volt reference voltage for all analog signal processing. this pin should be decoupled to gnda1 with 0.1 f capacitor. this pin becomes high impedance when the chip enters an analog power down mode. 4.2. analog interface pin name pin no. i/o function tg1 2 o this pin is the analog output of the first transmit input amplifier. it can be used to set the gain by external resistors. when the chip is in analog power down mode, this pin is high impedance. t1- 3 i this pin is the inverting input of the first transmit input amplifier. t1+ 4 i the non-inverting input of the first transmit input amplifier. note this pin may be connected to the vag pin for an inverting configuration if the input signal is referenced to the vag pin. tg2 9 o this pin is the analog output of the second transmit input amplifier. it can be used to set the gain by external resistors. when the chip is in analog power down mode, this pin is high impedance. t2- 8 i this pin is the inverting input of the second transmit input amplifier. t2+ 7 i the non-inverting input of the second transmit input amplifier. note this pin may be connected to the vag pin for an inverting configuration if the input signal is referenced to the vag pin. ro1 44 o this pin is the first non-inverting analog output of the receive smoothing filter. this pin can typically drive a 2k ? load to 1.579 volt peak referenced to the analog ground level. pi1 43 i this pin is the first inverting input to the po1- power amplifier. it is dc referenced to the vag pin. this pin and po1- are used to set the gain by using external resistors. po1- 42 o this pin is the first inverting power amplifier output. this pin can drive the a 300 ? load to 1.579 volt peak referenced to the vag pin.
w6612 publication release date: october 1998 - 5 - revision a1 4.2. analog interface, continued pin name pin no. i/o function po1+ 41 o this pin is the first non-inverting power amplifier output. this pin can drive the a 300 ? load to 1.579 volt peak referenced to the vag pin. ro2 11 o this pin is the second non-inverting analog output of the receive smoothing filter. this pin can typically drive a 2k ? load to 1.579 volt peak referenced to the analog ground level. pi2 12 i this pin is the second inverting input to the po1- power amplifier. it is dc referenced to the vag pin. this pin and po1- are used to set the gain by using external resistors. po2- 13 o this pin is the second inverting power amplifier output. this pin can drive the a 300 ? load to 1.579 volt peak referenced to the vag pin. po2+ 14 o this pin is the second non-inverting power amplifier output. this pin can drive the a 300 ? load to 1.579 volt peak referenced to the vag pin. 4.3. pcm serial interface pin name pin no. i/o function mclk 26 i this pin is the system master clock input pin. it is 2.048 mhz or 1.536 mhz. it must be synchronized with fst1, fst2 pin. fst1 32 i this pin is an 8 khz pulse for the first transmission of frame syncs. it enables the dt1 pcm output by bclkt1 pin. bclkt1 33 i this pin is the transmit bit clock. it shifts out the data on the dt1 pin on the rising edge. the frequency may vary from 128k to 4096 khz. dt1 31 o this pin is tri-state pcm output data for transmission controlled by fst1 and bclkt1 pin. nc 30 o no connection for reservation fsr1 28 i this pin is an 8 khz pulse to receive the first frame syncs. it enables the dr1 pcm input by bclkr1 pin. bclkr1 29 i this pin is the receive bit clock. it shifts data on the dr1 pin into the chip on the falling edge. the frequency varies from 128k to 4096 khz. dr1 27 i this pin is the pcm receive input data controlled by the fsr1 and bclkr1 pins. fst2 24 i this pin is an 8 khz pulse for the first transmission of frame syncs. it enables the dt1 pcm output by bclkt1 pin.
w6612 - 6 - 4.3. pcm serial interface, continued pin name pin no. i/o function bclkt2 25 i this pin is the transmit bit clock. it shifts out the data on the dt1 pin on the rising edge. the frequency may vary from 128k to 4096 khz. dt2 23 o this pin is tri-state pcm output data for transmission controlled by fst1 and bclkt1 pin. nc 22 o no connection for reservation fsr2 20 i this pin is an 8k hz pulse to receive the first frame syncs. it enables the dr1 pcm input by bclkr1 pin. bclkr2 21 i this pin is the receive bit clock. it shifts data on the dr1 pin into the chip on the falling edge. the frequency varies from 128k to 4096 khz. dr2 19 i this pin is the pcm receive input data controlled by the fsr1 and bclkr1 pins. pdi1 17 i it is power down for codec 1. when the pin is logic zero, all clocks for codec1 are off and all bias current for codec 1 turn off. pdi2 18 i this pin is power down for codec 2. when the pin is logic zero, all clocks for codec 2 are off and all bias current for codec 2 turn off. mode0 15 i this pin and mode1 pin can select the pcm output mode including a-law, mu-law, linear 14 bit pcm. mode1 16 i this pin and mode0 pin can select the pcm output mode including a-law, mu-law, linear 14 bit pcm. 4.4. miscellaneous pin name pin no. i/o function tst1 38 i this pin is internal pull-high test input pin. it is reserved by test mode. tst2 37 i this pin is internal pull-high test input pin. it is reserved by test mode. tst3 36 i this pin is internal pull-high test input pin. it is reserved by test mode.
w6612 publication release date: october 1998 - 7 - revision a1 5. block diagram -1 + - + - + - smoothing lpf sd adc sd dac -1 + - + - + - smoothing lpf sd adc sd dac 2.5 v ref. voltage 2.7 v regulator power supply management system dual sd codec-filter a/mu law expander a/mu law compressor serial data port (sdp) a/mu law expander a/mu law compressor serial data port (sdp) mode0 mode1 sequence and control po1+ po1- pi1 ro1 t1+ t1- tg1 po2+ po2- pi2 ro2 t2+ t2- tg2 vag vdsp mclk fsr1 bclkr1 dr1 fst1 bclkt1 dt1 fsr2 bclkr2 dr2 fst2 bclkt2 dt2 data conversion pdi1 pdi2 figure 5. winbond dual pcm ? codec block diagram 6. functional descriptions figure 5 illustrates the functional blocks of the winbond dual pcm ? codec. 6.1. power supply management system 6.1.1. power supply for all analog signals processing all analog circuits are supplied with vaa1 and vaa2, two 5 5% volt power supply. vaa1 power provides the first ? codec-filter and op amplifier; the vaa2 power provides the second ? codec- filter and op. amplifier. 6.1.2. power supply for all digital signals processing all digital circuits are supplied by the v dsp pin from a 2.7-volt regulator circuit. this reduces the chip power consumption. note that the v dsp pin should be decoupled to gnda with a 0.1 f capacitor and that this pin cannot be used for powering external loads.
w6612 - 8 - 6.1.3. reference voltage control system all analog signal reference voltages such as op amplifier is 2.5 volt. 6.2. sd codec-filter this device has built in dual linear 14-bit pcm codec-filter using ? technology. there are two paths in the block, a transmit path and a receive path. 6.2.1. transmit path in ? codec-filter the two analog signal inputs are passed to three terminal operational amplifiers (tg1, tg2) driving a typical 2 k ? load externally to amplify the input analog signal. then the ? adc converts the analog signal into linear 14-bit data. 6.2.2. receive path in ? codec-filter dual 14-bit linear digital signal from the digital conversion circuit is first passed to the ? dac block. it will convert the 14-bit samples to the analog signal. then the analog signal will reduce the spectral components of the switched capacitor filter by the analog smoothing filter. finally, the analog output signal is sent to the power amplifier, ro1 or ro2, which is capable of driving a 2k ? load connected to to the analog ground. note the device provides another power amplifier, po1 or po2, connected in a push-pull configuration. the po1 or po2 driver can accommodate large gain ranges by adjusting two external resistors for applications such as driving a telephone line or a handset receiver. 6.3. data conversion this block is the digital data convsersion circuit. there are two paths in this block, a transmit path and a receive path. 6.3.1. transmit path in the data conversion a linear 14 bit sample input from the transmit path of the ? codec-filter block is sent in two processing directions: a/mu law compressor, and linear conversion selected by mode1 and mode0 pin. the mode selection refers to table 6-1. in the a/mu law compressor, the 14 bit linear data will converted into 8-bit log-pcm. in the linear conversion, the 14-bit data will be sent into serial data port directly. the final result outputs the pcm signal through pin dt1 or dt2 under the control of the fst1 or fst2 (8k frame sync pulse) and bclkt1 or bclkt2 pins. the data output rate for bclkt1 or bclkt2 is from 128k to 4096 khz. mode selection mode1 pin mode0 pin a-law compressor/expander 0 0 mu-law compressor/expander 0 1 14-bit linear input/output 1 0 14-bit linear input/output 1 1 table 6-1 the mode selection for the data conversion 6.3.2. receive path in the data conversion the device receives pcm data from the dr1 or dr2 pin via the serial data port (sdp) under the control of the bclkr1 or bclkr2 and fsr1 or fsr2 pins. the clock of the receive frame sync fsr is 8 khz. the serial data rate in the bclkr1 or bclkr2 is from 128 khz to 4096 khz range.
w6612 publication release date: october 1998 - 9 - revision a1 the received pcm will be processed by two paths depended by the mode selection, see table 6-1. one path converts the 8-bit log-pcm into 14 bit linear pcm via a/mu law expander. the other one is sent 14 bit linear pcm directly. the finial 14-bit linear is sent into ? codec filter to convert into the analog signal. 6.3.3. frame sync. types the frame sync operation uses three industrial control types for the transfer of the pcm data words. these three types are the long frame sync , short frame sync and gci frame sync. 6.3.3.1. long frame sync the long frame sync types for various data rates are shown in figure 6-1 and 6-2. the bit rate for the pcm is determined by the mode selection mode1, mode0 pin, shown in table 6-1. the length of the frame sync is calculated by the number of falling edges at the bclkt1, bclkt2 or bclkr1, bclkr2 pin when the frame sync fst1, fst2 or fsr1, fsr2 pin is high.when the frame sync is held logic one for two consecutive falling edges of the bclkt1/2(bclkr1/2) , the device is in long frame sync mode. the device shifts out the data on the dt1 or dt2 pin at the bclkt1 or bclkt2 rising edge and shifts in the data on the dr1 or dr2 pin at the bclkr1 or bclkr2 falling edge. the pcm data remain low impedence until seven and a half data clock cycles for 64k bps if frame sync cycle is less than eight data clcok and thirteen and a half data clock cycles for 112 kbps if frame sync cycles is less than fourteen data clcok . after the data transmission, the dt1(dt2) outputs will return to high impedence state. the length of the frame sync may be changed on a frame by frame basis. 6.3.3.2. short frame sync the short frame sync types for 64 kbps or 112 kbps pcm, controlled by the mode1, mode0 pin. the timing is shown in figure 6-3 and 6-4. the length of the frame sync is equal to 1. the device shifts out data on the dt1 or dt2 pin at the bclkt1 or bclkt2 rising edge and shifts in data on the dr1 or dr2 pin at the bclkr1 or bclkr2 falling edge. the dt1(dt2) pin is going low impedance when the logic and of the fst1(fst2) pin and bclkt1(bclkt2) pin is the rising edge in the first. the pcm data remain low impedence until seven and a half data clock cycles for 64 kbps and thirteen and a half data clock cycles for 112 k bps. after the data transmission, the dt1(dt2) outputs will return to high impedence state. switching between long frame sync and short frame sync without going through a power down operation is not recommended. 6.3.3.3. gci(general circuit interface) frame sync the gci frame sync is for two b channels access interface in isdn application. the type is selected by bclkr1 pin when the bclkr1 pin is held low. this interface is only suitable for 8-bit log-pcm data, not 14-bit linear pcm data. the timing is shown in figure 6-5. the timing is controlled by 4 pins, fsc(fst1), dcl(bclkt1), dout(dt1), and din(dr1). the pulse length of the frame sync(fsc) is equal to 1 clock of dcl(bclkt1). the dcl(bclkt1) clcok rate is twice the actual pcm data rate. the pcm data for dout(dt1) or din(dr1) is two 8-bit b channel data, i.e., 16 dcl(bclkt1) clcok rate. the previous 8 bit data is for codec1 , and the left 8 bit data is for codec 2. the dout pin is going low impedance when the logic and of the fsc pin and dcl pin is high and remains the low impedance for 15 and 1/2 dcl cycles. note if the codec 1 enters the power down, the control timing is switched to the codec 2, fsc(fst2), dcl(bclkt2), dout(dt2), and din(dr2). meanwhile, the output of codec 1 part becomes the high impedance. if the codec 2 is power down, the output of codec 2 part becomes the high impedance.
w6612 - 10 - d7 bclkt1/bclkt2 (bclkr1/bclkr2) fst1/fst2 (fsr1/fsr2) 12 3 4 5 6 7 8 dt1/dt2 d6 d5 d4 d3 d2 d1 d0 msb lsb d7 d6 dr1/dr2 don't care don't care d5 d4 d3 d2 d1 d0 msb lsb figure 6-1 long frame sync for 64 kbps pcm timing d13 bclkt1/bclkt2 (bclkr1/bclkr2) fst1/fst2 (fsr1/fsr2) 1 2 3 4 dt1/dt2 d12 d11 d10 msb lsb 14 d2 d1 d0 12 13 dr1/dr2 don't care don't care msb lsb d2 d1 d0 d13 d12 d11 d10 figure 6-2 long frame sync for 112 kbps pcm timing bclkt1/bclkt2 (bclkr1/bclkr2) fst1/fst2 (fsr1/fsr2) 1 2 3 45 6 7 8 dt1/dt2 dr1/dr2 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb d7 d6 don't care don't care d5 d4 d3 d2 d1 d0 msb lsb figure 6-3 short frame sync for 64 kbps pcm timing
w6612 publication release date: october 1998 - 11 - revision a1 bclkt1/bclkt2 (bclkr1/bclkr2) fst1/fst2 (fsr1/fsr2) dt1/dt2 12 3 4 12 13 14 d13 d12 d11 d10 msb lsb d2 d1 d0 dr1/dr2 d13 d12 don't care don't care d11 d10 msb lsb d2 d1 d0 figure 6-4 short frame sync for 112 kbps pcm timing dcl(bclkt1) fsc(fst1) dout(dt1) msb lsb d7 channel 1 channel 2 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 din(dr1) msb lsb d7 channel 1 channel 2 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 figure 6-5 gci frame sync for 128 kbps pcm timing 6.4. sequence and control this block generates some internal clocks, providing clocks for ? codec-filter operation. the master clock mclk pin, which supports the clock of the digital circuit, may be asynchronous to all other blocks but synchronous to fst1 and fst2 frame sync pulse, 8 khz. its frequency is 2.048 mhz or 1.536 mhz. as for jitter tolerence of mclk pin, it is 146.5 ns for 2.048 mhz; but 260 ns for 1.536 mhz. in addition, the duty cycle of mclk pin must be 50% the rising edge of mclk pin must be approximately aligned with the rising edge of the fst1 or fst2 pin depent on whether the codec of device is power down. if the device does not enter the power down mode, the master clock is refered to fst1 in default . if the codec1 is power down, the master clock is refered to fst2 pin. the device will automatically detect the clock rate of mclk pin by a prescaler circuit for mclk and fst1 (or fst2). when the codec is start-up initially such as power-on reset or power-up after power-down, the steady codec output data will be delay by about 60 samples. when the pdi1 pin is held to logic 0, the codec 1 will become the hardware power down. the vag, tg1, ro1, po1, dt1 outputs enter high impedance. when the pdi2 pin is held to logic 0, the codec 2 will become the hardware power down. the tg2, ro2, po2, dt2 outputs are all high impedance. if the device is gci mode , the channel can be powered down separatedly by pdi1 or pdi2 pin. the device is built-in power-on reset circuit in default .
w6612 - 12 - 6.5. i/o level digital i/o for the device can be programmed in either mu-law or a-law for log-pcm mode. full scale and zero words for these two log-pcm forms are shown in table 6-2. for analog signal processing, the maximum transmit level is 3.17 dbm0 for mu-law or 3.14 dbm0 for a-law. these values meet the ccitt g.711specifications. mu-law a-law level sign segment bits step bits sign segment bits step bits + max. scale 1 000 0000 1 010 1010 +zero 1 111 1111 1 101 0101 - zero 0 111 1111 0 101 0101 - max. scale 0 000 0000 0 010 1010 table 6-2 full scale and zero word for mu/a-law 7. electrical characteristics 7.1. absolute maximum ratings (voltage referenced to gnda1, gnda2, and gndd pin) parameter symbol rating unit power supply voltage vaa1, vaa2, v dd -0.3 to 6.0 v analog input/output voltage --- -0.3 to vaa1(vaa2) + 0.3 v digital input/output voltage --- -0.3 to v dd +0.3 v operating temperature t op -40 to +85 c storage temperature t stg -85 to +85 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability o f the device. 7.2. dc characteristics (gnda1 = gnda2 = gndd = 0 volt ; t op = -40 to +85 c) parameter sym. condition min. typ. max. uni t operating voltage vdd, vaa1, vaa2 ---- 4.75 5.0 5.25 v operating current iop mclk = 2.048 mhz, no load (vaa1 = vaa2 = 5v) --- 19 -- ma power down current i pwdn mclk/pdi off, no load --- --- 0.3 ma input high voltage v ih all digital input pins v dd -0.5 --- ----- v input low voltage v il all digital input pins 0 ---- 0.5 v output high voltage v oh dt1, dt2 v dd -0.5 ---- ----- v output low voltage v ol dt1, dt2 0 --- 0.4 v input high current i il gndd vin v dd -10 --- +10 a input low current i ih gndd vin v dd -10 --- +10 a
w6612 publication release date: october 1998 - 13 - revision a1 7.3. analog transmission characteristics (vaa1 = vaa2 = +5v 5%, gnda1 = gnda2 = 0 volt , top = -40 to +85 c ; all analog signal referenced to vag; 64 kbps log- pcm; fst1(fst2) = fsr1(fsr2) = 8 khz; bclkt1(bclkt2) = bclkr1(bclkr2) = 2.048 mhz; mclk = 2.048 mhz synchronous with fst1(fst2) ; unless otherwise noted) 7.3.1. amplitude response for analog transmission performance parameter sym. condition typ. transmit receive unit min. max. min. max. absolute level l abs 0 dbm0 = +0 dbm @ 600 ? 1.096 --- --- --- --- vpk max. transmit level t xmax 3.17 dbm0 for mu-law 3.14 dbm0 for a-law 1.579 1.573 --- --- --- --- --- --- --- --- vpk vpk frequency response, relative to 0 dbm0 @ 1020hz g rtv 15 hz 50 hz 60 hz 200 hz 300 to 3000 hz 3300 hz 3400 hz 4000 hz 4600 to 100, 000 hz ---- ---- --- --- --- --- --- --- --- ---- --- --- -1.0 -0.20 -0.35 -0.8 --- --- -40 -30 -26 -04 +0.15 +0.15 0 -14 -32 -0.5 -0.5 -0.5 -0.5 -0.20 -0.35 -0.8 --- --- 0 0 0 0 +0.15 +0.15 0 -14 -30 db gain variation vs. level tone (1020 hz relative to -10 dbm0) g lt +3 to -40 dbm0 -40 to -50 dbm0 -50 to -55 dbm0 --- --- --- -0.3 -1.0 -1.6 +0.3 +1.0 +1.6 -0.2 -0.4 -0.8 +0.2 +0.4 +0.8 db 7.3.2. distortion characteristics for analog transmission performance parameter sym. condition typ. transmit receive unit min. max. min. max. absolute group delay d abs 1600 hz --- --- 440 --- --- s total distortion vs. level tone (1020 hz, mu-law, c- message) d lt +3 dbm0 0 to -30 dbm0 -40 dbm0 -45 dbm0 --- --- --- --- 36 36 29 25 --- --- --- --- 34 36 30 25 --- --- --- --- dbc
w6612 - 14 - 7.3.3. noise characteristic for analog transmission performance parameter sym. condition typ. transmit receive unit min. max. min. max. idle channel with equipment noise n ide mu-law, c-message --- --- +5 --- +13 dbrn spurious out-of-band at spko (300 to 3400 hz @ 0 dbm0) n spo 4600 to 7600 hz 7600 to 8400 hz 8400 to 100,000 hz --- --- --- --- --- --- --- --- --- --- --- --- -30 -40 -30 db in-band spurious (1020 hz @ 0 dbm0) n ibs 300 to 3000 hz --- --- -47 --- -47 db crosstalk (1020 hz @ 0 dbm0) n ctk 300 to 3000 hz --- --- -70 --- -70 db 7.4. analog electrical characteristics (op amplifer tg1, tg2, ro1, ro2; power amplifer po1, po2; vaa1 = vaa2 = +5v 5%, gnda1 = gnda2 = 0v; top = -40 to +85 c) parameter sym. conditions min. typ. max. unit input offset voltage of tg1, tg2 v ofin t1+, t1-, t2+, t2- --- --- 25 mv load capacitance for ro1, ro2 c lro ro1, ro2 --- --- 100 pf load resistance for ro1,ro2 r ldro ro1, ro2 2 --- --- ? load resistance for tg1,tg2 r ldtg tg1, tg2 2 --- --- k ? vag output voltage v ag to gnda1, gnda2 2.3 2.5 2.6 v power supply rejection ratio (0 to 100 khz @ 100m vrms to vaa1(vaa2) with c-message) psrrdd tg1, tg2 --- 40 --- dbc load capacitance for po1, po2 clpo po- to po+ --- ---- 150 pf load resistance differentially for po1, po2 rldpo po- to po+ 300 --- ---- ? input offset voltage for pi vofpi ref to vag --- ---- 25 mv
w6612 publication release date: october 1998 - 15 - revision a1 7.5. digital switching characteristics 7.5.1 long frame and short frame sync timing (v dd = 5 5% v; gndd = 0v; all digital circuits referenced to gndd; top = -40 to +85 c, c l = 150 pf ) parameter sym. conditions min. typ. max. unit master clock frequency t mast mclk ---- 2.048 1.536 ---- mhz mhz bit clock frequency t bclk bclkt1, bclkt2, bclkr1, bclkr2 128 --- 4096 khz frame sync. frequency t sync fst1, fst2, fsr1, fsr2 --- 8 - - khz clock duty cycle d c mclk, bclkt1, bclkt2, bclkr1, bclkr2 --- 50 --- % rise time t ir all digital input pins --- --- 50 ns fall time t if all digital input pins --- --- 50 ns hold time for 2nd cycle of bclkt1/2(bclkr1/2) t hld bclkt1/2(bclkr1/2) low to fst1/2(fsr1/2) low 50 --- --- ns transmit sync. timing t xs t sx bclkt1/2 to fst1/2 fst1/2 to bclkt1/2 20 80 --- --- --- --- ns receive sync. timing t rs t sr bclkr1/2 to fsr1/2 fsr1/2 to bclkr1/2 20 80 --- --- --- --- ns setup time for dr1(dr2) valid t stdr --- 20 --- --- ns hold time for dr1(dr2) valid t hddr --- 50 --- --- ns output delay time for 1st dt1(dt2) valid t dv1 bclkt1/2 to dt1/2 10 --- 120 ns output delay time for 2nd dt1(dt2) valid t dv2 bclkt1/2 to dt1/2 10 --- 120 ns output delay time for dt1(dt2) high impedance t dhi bclkt1/2 to dt1/2 10 --- 120 ns note: these parameters are shown in figure 7-1 and 7-2.
w6612 - 16 - mclk tmast fst1/fst2 bclkt1/bclkt2 dt1/dt2 tsync 1 2 3 4 5 6 7 8 tir tif txs tsx tdv2 thld 9 d7 d6 msb lsb d5 d4 d3 d2 d1 d0 fsr1/fsr2 bclkr1/bclkr2 dr1/dr2 tsync 1 23 4 56 7 8 trs tsr thddr tstdr 8 thld d7 d6 msb lsb d5 d4 d3 d2 d1 d0 tdv1 tdv1 tdhi tdhi figure 7-1 long frame sync timing fst1/fst2 bclkt1/bclkt2 tsync 1 2 3 4 5 6 7 txs tsx tdv2 8 dt1/dt2 lsb d7 dr1/dr2 tsync 12 3 45 6 7 trs tsr thddr tstdr d6 d5 8 fsr1/fsr2 bclkr1/bclkr2 d4 msb lsb d3 d2 d1 d0 d7 d6 d5 d4 msb d3 d2 d1 d0 tdstx tdv1 tdhi figure 7-2 short frame sync timing
w6612 publication release date: october 1998 - 17 - revision a1 7.5.2 gci frame sync timing (v dd = 5 5% v; gndd = 0v; all digital circuits referenced to gndd; top = -40 to +85 c, c l = 150 pf ) parameter sym. conditions min. typ. max. unit bit clock frequency t dcl dcl (bclkt1) 512 --- 4096 khz frame sync. frequency t fsc fsc(fst1) --- 8 - - khz setup time for din(dr1) valid t stdin --- 20 --- --- ns hold time for din(dr1) valid t hddin --- 50 --- --- ns output delay time for dout(dt1) valid t dv dcl to dout 10 --- 60 ns output delay time for dout(dt1) high impedance t dhi dcl to dout 10 --- 60 ns note: these parameters are shown in figure 7-3 dcl(bclkt1) fsc(fst1) dout(dt1) msb lsb d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 tdv din(dr1) msb lsb d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 tstdin thddin 1 23 45 6 7 8 9 10 11 12 13 14 15 16 tdv tdhi 1718 19 20 2122 23 24 25 26 27 28 29 30 31 32 tdhi figure 7-3 gci frame sync timing
w6612 - 18 - 8. application information for the transformer application, vaa1 = vaa2 = v dd = +5v 5% the application circuit, figure 8-1 is as follows. 150 w r0 = 600 w tip n = 0.5 n = 1 ring 6 5 4 3 2 1 28 29 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 150 w r0 = 600 w tip n = 0.5 n = 1 ring 20k 20k 10k 10k 0.1 uf 10k 10k 20k 20k 0.1 uf mode0 mode1 pcm_2 in 8k hz 128--4096 khz vdd pcm_2 out 8k hz 128--4096 khz mclk=2.048 or 1.536 m pcm_1 in 8k hz 128--4096 khz nc pcm_1 out 8k hz 128--4096 khz w6612 (pqfp) vaa1 vaa2 nc pdi1 pdi2 figure 8-1 typical transformer application
w6612 publication release date: october 1998 - 19 - revision a1 for the slic(subsciber line interface circuit) application, vaa1 = vaa2 = v dd = +5v 5% the application circuit, figure 8-2 is as follows. 6 5 4 3 2 1 28 29 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 10k 10k 10k 10k 0.1 uf 10k 10k 10k 10k 0.1 uf mode0 mode1 pcm_2 in 8k hz 128--4096 khz vdd pcm_2 out 8k hz 128--4096 khz mclk = 2.048 or 1.536 m h pcm_1 in 8k hz 128--4096 khz pcm_1 out 8k hz 128--4096 khz 16 19 vtx rsn 562k 20k 300k 18k pbl3860 1uf 1uf 16 19 vtx rsn 562k 20k 300k 18k pbl3860 1uf 1uf w6612 (pqfp) vaa1 vaa2 nc n c pdi1 pdi2 figure 8-2 typical slic application
w6612 - 20 - 9. package dimensions 6 5 4 3 2 28 29 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2122 23 24 25 26 27 a b cd 44-pin pqfp 1 e e figure9-1 44-lead plcc package symbol dimension in inch dimension in mm a 0.52 13.2 b 0.394 10.0 c 0.394 10.0 d 0.52 13.2 e 0.031 0.8 e 0.091 2.3
w6612 publication release date: october 1998 - 21 - revision a1 headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792697 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-7197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2730 orchard parkway, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-9436668 note: all data and specifications are subject to change without notice.

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